ESE 382
4 credits
Digital system design using the hardware description language VHDL and system implementation using complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). Topics include design methodology, VHDL syntax, entities, architectures, testbenches, subprograms, packages, and libraries. Architecture and characteristics of PLDs and FPGAs are studied. Laboratory work involves writing the VHDL descriptions and testbenches for designs, compiling, and functionally stimulating the designs, fitting and timing simulation of the fitted designs, and programming the designs into a CPLD or FPGA and bench testing.
ESE or ECE major; ESE 118 or permission of instructor
| Section | Days | Time | Room | Instructor |
|---|---|---|---|---|
| LEC 01 | TuTh | 12:30PM–1:50PM | LGT ENGR LAB 102 WESTCAMPUS | Kenneth Short★ 3.5 |
| LAB L01 | We | 8:30AM–11:20AM | LGT ENGR LAB 228 WESTCAMPUS | Kenneth Short★ 3.5 |
| LAB L02 | We | 2:00PM–4:50PM | LGT ENGR LAB 228 WESTCAMPUS | Kenneth Short★ 3.5 |
| LAB L03 | Th | 8:30AM–11:20AM | LGT ENGR LAB 228 WESTCAMPUS | Kenneth Short★ 3.5 |
| LAB L04 | Fr | 8:30AM–11:20AM | LGT ENGR LAB 228 WESTCAMPUS | Kenneth Short★ 3.5 |